CLKPOL=IDLELOW, MPM=DISABLE, SYNC=DISABLE, CSINV=DISABLE, ERRSDMA=DISABLE, CLKPHA=SAMPLELEADING, RXINV=DISABLE, OVS=X16, LOOPBK=DISABLE, ERRSRX=DISABLE, BYTESWAP=DISABLE, AUTOTRI=DISABLE, TXBIL=EMPTY, ERRSTX=DISABLE, TXINV=DISABLE, CSMA=NOACTION, CCEN=DISABLE, MSBF=DISABLE
No Description
| SYNC | USART Synchronous Mode 0 (DISABLE): The USART operates in asynchronous mode 1 (ENABLE): The USART operates in synchronous mode |
| LOOPBK | Loopback Enable 0 (DISABLE): The receiver is connected to and receives data from U(S)n_RX 1 (ENABLE): The receiver is connected to and receives data from U(S)n_TX |
| CCEN | Collision Check Enable 0 (DISABLE): Collision check is disabled 1 (ENABLE): Collision check is enabled. The receiver must be enabled for the check to be performed |
| MPM | Multi-Processor Mode 0 (DISABLE): The 9th bit of incoming frames has no special function 1 (ENABLE): An incoming frame with the 9th bit equal to MPAB will be loaded into the receive buffer regardless of RXBLOCK and will result in the MPAB interrupt flag being set |
| MPAB | Multi-Processor Address-Bit |
| OVS | Oversampling 0 (X16): Regular UART mode with 16X oversampling in asynchronous mode 1 (X8): Double speed with 8X oversampling in asynchronous mode 2 (X6): 6X oversampling in asynchronous mode 3 (X4): Quadruple speed with 4X oversampling in asynchronous mode |
| CLKPOL | Clock Polarity 0 (IDLELOW): The bus clock used in synchronous mode has a low base value 1 (IDLEHIGH): The bus clock used in synchronous mode has a high base value |
| CLKPHA | Clock Edge For Setup/Sample 0 (SAMPLELEADING): Data is sampled on the leading edge and set-up on the trailing edge of the bus clock in synchronous mode 1 (SAMPLETRAILING): Data is set-up on the leading edge and sampled on the trailing edge of the bus clock in synchronous mode |
| MSBF | Most Significant Bit First 0 (DISABLE): Data is sent with the least significant bit first 1 (ENABLE): Data is sent with the most significant bit first |
| CSMA | Action On Chip Select In Main Mode 0 (NOACTION): No action taken 1 (GOTOSLAVEMODE): Go to secondary mode |
| TXBIL | TX Buffer Interrupt Level 0 (EMPTY): TXBL and the TXBL interrupt flag are set when the transmit buffer becomes empty. TXBL is cleared when the buffer becomes nonempty. 1 (HALFFULL): TXBL and TXBLIF are set when the transmit buffer goes from full to half-full or empty. TXBL is cleared when the buffer becomes full. |
| RXINV | Receiver Input Invert 0 (DISABLE): Input is passed directly to the receiver 1 (ENABLE): Input is inverted before it is passed to the receiver |
| TXINV | Transmitter output Invert 0 (DISABLE): Output from the transmitter is passed unchanged to U(S)n_TX 1 (ENABLE): Output from the transmitter is inverted before it is passed to U(S)n_TX |
| CSINV | Chip Select Invert 0 (DISABLE): Chip select is active low 1 (ENABLE): Chip select is active high |
| AUTOCS | Automatic Chip Select |
| AUTOTRI | Automatic TX Tristate 0 (DISABLE): The output on U(S)n_TX when the transmitter is idle is defined by TXINV 1 (ENABLE): U(S)n_TX is tristated whenever the transmitter is idle |
| SCMODE | SmartCard Mode |
| SCRETRANS | SmartCard Retransmit |
| SKIPPERRF | Skip Parity Error Frames |
| BIT8DV | Bit 8 Default Value |
| ERRSDMA | Halt DMA On Error 0 (DISABLE): Framing and parity errors have no effect on DMA requests from the USART 1 (ENABLE): DMA requests from the USART are blocked while the PERR or FERR interrupt flags are set |
| ERRSRX | Disable RX On Error 0 (DISABLE): Framing and parity errors have no effect on receiver 1 (ENABLE): Framing and parity errors disable the receiver |
| ERRSTX | Disable TX On Error 0 (DISABLE): Received framing and parity errors have no effect on transmitter 1 (ENABLE): Received framing and parity errors disable the transmitter |
| SSSEARLY | Synchronous Secondary Setup Early |
| BYTESWAP | Byteswap In Double Accesses 0 (DISABLE): Normal byte order 1 (ENABLE): Byte order swapped |
| AUTOTX | Always Transmit When RX Not Full |
| MVDIS | Majority Vote Disable |
| SMSDELAY | Synchronous Main Sample Delay |